Iron contamination is known as a yield limiting factor during silicon device manufacturing. Thermal oxide iron contamination leads to oxide degradation and decreases the oxide breakdown voltage. Once diffused into the silicon bulk, iron creates deep-level recombination centers, reducing the carrier lifetime and causing device malfunctions. See A. A. Isratov, H. Hieslmair, and E. R. Weber, Appl. Phys. A: Mater. Sci. Process. 70, 489 (2000); and A. A. Isratov, H. Hieslmair, and E. R. Weber, Appl. Phys. A: Mater. Sci. Process. 69, 13 (1999).
Iron contamination during thermal processing originates from two major sources: iron diffusion from the wafer surface contaminated before thermal processes and iron cross contamination from the hardware components during thermal processing. See I. Rapoport, P. Taylor, B. Orschel, and J. Kearns, AIP Conf. Proc. 772, 103 (2005). High-resolution surface photovoltage (SPV) iron mapping is frequently employed to track the metal contamination sources. See G. Zoth and W. Bergholz, J. Appl. Phys. 67, 1 (1990); and A. Cacciato, S. Vleeshouwers, and S. Evseev, J. Electrochem. Soc. 145, 701 (1998).
SPV method accuracy improvements were implemented developing the Digital SPV method to enable the Fe detection limit within the 108 atom/cm3 range. See M. Wilson, A. Savtchouk, I. Tarasov, J. D'Amico, P. Edelman, N. Kochey and J. Lagowski, ECS Trans. 2008 16(6): 285-301
As thermal budgets are continually reduced for device processing, iron contaminants accumulate close to the wafer surface where the iron is initially introduced. Measuring the Two-Side SPV is an effective means for monitoring iron contamination after thermal processing. See I. Rapoport, P. Taylor, J. Kearns, and D. K. Schroder, J. Appl. Phys. 107, 013518 (2010).